Dynamic CMOS Divider 2.4GHz
Divider is the PLL circuit, the basic unit. Is working at the highest frequency PLL unit circuit. Traditional divider used advanced high-speed process technology. Such as bipolar, GaAs, SiGe, and crafts. As CMOS device dimensions become smaller and smaller, can be deep sub-micron CMOS process manufactures high-speed divider. As low-cost CMOS devices, high-speed CMOS frequency divider which has broad market prospects. The author gives one kind of manufacturing process using O.6μvmCMOS 2.4GHz dual-mode dynamic pre-divider, the maximum input frequency divider can reach 3GHz.
2 divider circuit structure
PLL and prescaler structure shown in Figure 1. VCO's output directly to level 1 ÷ 2 divider circuit connected to the divider in the frequency of which is the highest part of the most difficult part of the design. Then the signal into the ÷ 4 / 5 dual-modulus prescaler, the part of the circuit's frequency is still high modulus choice except to swallow counter from the static control. ÷ 4 / 5 the principle of the circuit shown in Figure 2, when MC = 1, the divider mode 4, the contrary is 5.
Dynamic CMOS Divider 2.4GHz
3 cell circuit
3.1 Level 1 ÷ 2 circuit
3.1.1 3 typical frequency circuit
In the PLL. Level 1 the highest frequency divider. In recent years, widely used abroad, high-speed CMOS frequency divider circuits are mainly three kinds. The first one kind of static SCL circuit (see Figure 3), the evolution from the ECL circuit, and compared to traditional static frequency divider, as the circuit's swing low, thus the circuit to work fast; section 2 are dynamic TSPC circuits, single-phase clock (TSPC) circuit technology, which constitute the sub-frequency circuits reduce the number of components, so as to improve the working speed, low power consumption while this circuit, the classical structure in Figure 4 (a) shows The nine DFF. J. Navarro on the basis of the TSPC technique proposed in 1997, E-TSPC technique; No. 3 is the injection locking (injected-locked) circuit, due to use of inductors, and so its size is too large and the process difficult and rarely been widely used.
Typical SCL2 divider including the tail current source and the source load, including needs 20 transistors (see Figure 3), the crystal can not be small, so the input capacitance of great or even more than control their own input capacitance, leading to the VCO and SCL frequency circuit plus buffer; In addition, the work of the former two in the high frequency divider will be half the total power dissipation. Thus SCL divider phase locked loop in terms of total power consumption is high. Single-phase clock (TSPC) In addition to high frequency circuit, the small number of transistors and small size, it consumes very little power, so often used in the prescaler. TSPC divider noise performance is not good enough, because it is a dynamic single-ended structure, so the impact of noise than the differential of the SCL circuits easily. The specific circuit structure should be adopted, as the case may be. Parameters in O.6um conditions, SCL ÷ 2 frequency divider circuits, the maximum operating frequency is only 910MHz, power consumption is 12mW; I designed using 0.6um technology TSPC ÷ 2 divider circuit in the power supply voltage of 5V, the frequency of up to 3GHz, power only 2mW.
Dynamic CMOS Divider 2.4GHz
3.1.2 the specific circuit
Design Level 1 ÷ 2 divider structure shown in Figure 4 (b) below. It is the improved traditional TSPC. This circuit changes the signal circuit. Purpose is to reduce the internal node capacitance, increased pace of work. After adjusting the size of each transistor, the circuit operating frequency range of 2GHz-3GHz. Compared with the SCL, TSPC only 9 transistors, and the desirability of the minimum gate length (0.6um). Source current through the circuit simulation can be seen close, less transistors. Low power of the circuit.
3.2 dual-mode prescaler circuit
Figure 5 (a) shows the ÷ 2 / 3 dual-mode prescaler circuit logic. Synchronous work, the specific circuit shown in Figure 5 (b) below. The E-TSPC circuit technique, compared to the traditional gate, while an increase of two transistors, but the faster switching; and in single-well process conditions. Effect of non-receptor circuit. As a result of TSPC technique, gate length remains at 0.6um. For the subsequent one of the ÷ 2 and ÷ 32 circuit, because the operating frequency has been greatly reduced. Can work in asynchronous mode, so simply Figure 4 (b) ÷ 2 as shown in the circuit unit can be connected in series. The simulation shows that the circuit meets the design requirements.
Dynamic CMOS Divider 2.4GHz
4 Simulation waveforms and circuit characteristics
CMSC company with double-layer metal CMOS 0.6um n trap model of circuit emulation and simulation. Simulation tool is Syn-opsys company Hspice and Agilent's ADS.
The minimum input signal amplitude divider is in the right premise of the output obtained. Also known as the input signal sensitivity. With the power supply voltage drop, the work of the highest frequency divider down very quickly, which can be seen as relatively low-pressure environment TSPC SCL disadvantage. Simulation results show that the rate of at least 1.2V input to make the circuit work in the 3GHz. The operating frequency in the 2.4GHz or so. Only less than 200mV of signal amplitude, indicating that the circuit can be used in the 2.4GHz ISM band.
Table 1 lists the parameters of the divider divider described in literature with several parameters of contrast. All of the divider are used CMOS technology. The main parameter is the process more, the maximum input frequency, supply voltage and power consumption.
Dynamic CMOS Divider 2.4GHz
5 Conclusion
Using O. 6μm CMOS process design, which adopts TSPC and E-TSPC technique of dynamic dual-modulus prescaler. Can work in the 2.4GHz ISM band, the maximum operating frequency up to 3GHz. Divider at high frequencies small parasitic capacitance. Supply voltage of 5V, the power consumption of about 8mW. Frequency of 2.4GHz, the input signal amplitude is only 190mV, can be used in 2.4GHz ISM band PLL or frequency synthesizer circuit.