CAN Bus System Design and Implementation
Emergence of the concept in the field bus to the current nearly 20 years, there have been several field bus technology and mature. CAN bus which has been recognized as some of the most promising one field bus. CAN is a CAN controller with the composition of the high-performance serial data communication local area networks, is the most widely used international fieldbus one. Initially, CAN was designed as a vehicle environment, micro-controller communications, in-vehicle electronic control unit ECU the exchange of information between the formation of automotive electronic control network. As the Qi with communication speed, reliability and cost performance good Deng Gao Tuchuyoudian, the more and greater Tazheng widely used in automotive, 机械 industry, textile machinery, agricultural machinery, Ji Qiren, NC 机床, medical equipment, home the fields of electrical appliances and sensors. Figure 1 shows a typical system block diagram CAN bus node.
CAN Bus System Design and Implementation
System hardware design
SJA1000 CAN controller is an independent company PCA82C200CAN PHILIPS alternative controller, which is fully compatible with PCA82C200 basis, adding a new mode of PeliCAN, SJA1000 has many new features full support for the CAN2.0B agreement. SJA1000 work patterns through its internal clock divider registers to select the CAN mode. SJA1000 can support a variety of timing characteristics of the processor, such as the Intel models, or Motorla mode, SJA1000 and the microprocessor interface is very simple microprocessor to access the external memory means to access the SJA1000.
TJA1050 is the Controller Area Network CAN protocol controller and the physical bus interface between, TJA1050 can send a bus to provide different performance for the CAN controller receives a different performance. TJA1050 has following features: full compliance with ISO 11898 standards, the most high-speed to reach 1Mb / s, 3.3V and 5V input stage device is compatible, at least 110 nodes can be connected. The design of the microprocessor 89C51 responsible for initializing the SJA1000 and SJA1000 to achieve by controlling the receive and transmit data such as communication tasks, the system schematic shown in Figure 2.
CAN Bus System Design and Implementation
CAN controller SJA1000 data lines AD0 ~ AD7 connected to Microcontroller 51 P0 port, connected to the base address for the 0xFA00 external memory chip select signal, when the access address 0xFA00 ~ 0xFA31 time, CPU can perform the appropriate read and write operations SJA1000. SJA1000, and, respectively, corresponding with the 51 pin connected, then 51 to 51 can interrupt access SJA1000.
System software design
The design of the system consists of four nodes, one node from the host computer through the parallel port data transfer CAN bus transceivers constitute the other three nodes shown in Figure 2, the system constitutes a single chip CAN bus transceiver. SCM system to send a second (8 bytes) data. Connect PC to CAN bus transceiver corresponding PC test software support, this article introduces the CAN bus transceiver microcontroller programming. Figure 3 is a flow chart of lower computer software.
CAN Bus System Design and Implementation
System design, part of the code is as follows:
main ()
(
Sja_1000_Init (); / / initialize the SJA1000
Init_Cpu (); / / initialize the CPU
Init_T0 (); / / initialize timer
flag_init = 0x00;
while (1)
(
if (rcv_flag) / / rcv_flag to accept the flag, to receive the single chip processor
(
rcv_flag = 0; BCAN_DATA_RECEIVE (rcv_data);
BCAN_CMD_PRG (0X04);
disp_rec ();
)
if (flag_sec) / / timer interrupt flag is, time is the time to send data frame
(Flag_sec = 0; send_data [0] = 0xaa; send_data [1] = 0x08; send_data [2] = DA1;
send_data [3] = DA2;
send_data [4] = DA3;
send_data [5] = DA4;
send_data [6] = DA5;
send_data [7] = DA6;
send_data [8] = DA7;
send_data [9] = DA8; BCAN_DATA_WRITE (send_data); BCAN_CMD_PRG (0X01);
)
if (err_flag)
(
err_flag = 0;
disp_err ();
Sja_1000_Init ();
)
display (a); / / loop which show data
SJA1000 initialization process includes the application into the reset state, set the bus baud rate, set the output mode, open the error interrupt, receive and send interrupts. Data packets sent during the first two bytes 0Xaa, 0X08 for the descriptor, including 11 long ID (identifier) 1 RTR4-bit data length of the DLC were described in 16. BCAN_DATA_RECEIVE (rcv_data), the 89C51 on the SJA1000 read data function of its specific function definition:
bit BCAN_DATA_RECEIVE (unsigned char * RcvDataBuf)
(
unsigned char TempCount;
SJA_BCANAdr = REG_STATUS; / / access point status register address
if ((* SJA_BCANAdr & 0x01) == 0) / / determine the effectiveness of packet
(
return 1;
)
SJA_BCANAdr = REG_RxBuffer2; / / access point to receive buffer 2 address
if ((* SJA_BCANAdr & 0x10) == 0) / / If the data frame
(
TempCount = (* SJA_BCANAdr & 0x0f) 2; / / calculate the number of data packets
)
else
(
TempCount = 2;
)
SJA_BCANAdr = REG_RxBuffer1; / / access point to receive buffer address 1
memcpy (RcvDataBuf, SJA_BCANAdr, TempCount); / / read receive buffer packets
return 0;
)
CAN controller, this function is limited to receiving data, the return value is 0 if successful acceptance, if accepted as a failure.
BCAN_DATA_WRITE (send_data) function is 89C51 write data on the SJA1000 specific function is defined as follows:
bit BCAN_DATA_WRITE (unsigned char * SendDataBuf)
(
unsigned char TempCount;
SJA_BCANAdr = REG_STATUS; / / access point status register address
if ((* SJA_BCANAdr & 0x08) == 0) / / determine whether the completion of the last send
(
return 1;
)
if ((* SJA_BCANAdr & 0x04) == 0) / / determine whether to send the buffer lock
(
return 1;
)
SJA_BCANAdr = REG_TxBuffer1; / / access point to send the address of buffer 1
if ((SendDataBuf [1] & 0x10) == 0) / / determine RTR, and thus come to a data frame or remote frame
(
TempCount = (SendData Buf [1] & 0x0f) 2; / / input data frame
)
else
(
TempCount = 2; / / Remote Frame
memcpy (SJA_BCANAdr, SendDataBuf, TempCount);
return 0;
)
This function will be sent to specific kinds of data frames, send buffer into the SJA1000, and then start, the function returns 0 to send data successfully sent to the buffer, return to the previous one that the data is being sent.
System is relatively easy to network nodes only to hang on the same twisted pair can start the host computer of the CAN transceiver is used to monitor the status of bus data. When starting a lower machine CAN transceiver test PC software can receive every one second by the same CAN transceiver to send data frames. Experimental results show that when the three Slave CAN bus also made the receiver when the number of data loss and no data bus conflict phenomenon.
Conclusion
Fieldbus has great development potential, it will change to the field of automatic control far-reaching implications. We designed the CAN bus transceiver is universal, in the system design based on only the appropriate data transmission protocol can be applied to modify various CAN bus data transfer system.