SHARC DSP with the SJA1000 CAN-bus interface
Abstract: This paper discusses the DSP and the CAN controller SJA1000 bus interface differences, proposed SJA1000 and the SHARC DSP family of simple interface design methods and general methods. Tests show that this method has good stability, high transmission efficiency.
Introduction
Currently, there are a number of CAN controllers will microprocessor embedded into a system, but there are still a lot of people are not familiar with CAN controller microprocessor. Combined use of microprocessors and CAN controller design to be necessary, and, CAN controller with CAN bus communication protocol to complete all the necessary functions required, therefore, CAN controller interface with other microprocessor design a CAN bus system design priority. This article focuses on the core with SHARC DSP, based on SJA1000 CAN-bus interface.
SHARC DSP with the SJA1000 CAN-bus interface
Figure 1 SJA1000 and CAN bus connection
SHARC DSP with the SJA1000 CAN-bus interface
Figure 2 ADSP21062 and simplified design SJA1000
SHARC DSP with the SJA1000 CAN-bus interface
Figure 3 CPLD-based design ADSP21062 and SJA1000
SHARC DSP with the SJA1000 CAN-bus interface
Figure 4 CPLD logic diagram
About SJA1000
SJA1000 is a stand-alone CAN controller, for moving targets and general industrial environments Controller Area Network (CAN). It is the company's early Philips CAN controller PCA82C200 (Basic CAN) alternatives, but also adds a new mode (PeliCAN), this model has many new features to support the CAN2.0B agreement.
SJA1000 interface with the microprocessor by the eight major time-multiplexed data and address lines to complete: AD0 ~ AD7, ALE / AS,, / E,,, MODE, and, where MODE select signal for the interface mode can be set to Intel or in Motorola mode. The difference is: Intel mode, the processor on the SJA1000 to write, use, as read, write data signals, ALE falling edge latches address (address signal at this time to guarantee the basic set up to keep time), only in reading, writing data low; Motorola mode, read, write signal with distinction (high read, low write), with / E data strobe (falling edge latched), AS and CS is similar to the ALE and Intel. Popular MCS51/96 MCU provides a convenient way of direct interface to Intel, for general considerations, it describes the interface design is based on Intel models.
DSP interface signals and timing
Difference with earlier processors, DSP chips are pin-chip address lines and data lines by separating the design, without using time-multiplexed address data line, and no ALE signal, so give CAN controller and the DSP made it difficult to interface, and different DSP external pins and timing are slightly different. CAN controller and the DSP to design the interface, we must first compare the timing DSP and CAN controller.
This optional DSP-ADSP21062, clocked at 40MHz, single-cycle (zero wait) to access memory, the required memory response (read or write) cycle is less than 17ns, but many of the response speed of memory or peripherals not so fast, so should be extended by adding wait to visit. Wait ADSP2106x supports two ways, namely, to wait (soft wait) and wait outside (hard to wait).
SJA1000 and the CAN bus connection
Select 82C250 as a transceiver, select 6N137 optical isolators to achieve high-speed CAN bus system and isolation. The connection method shown in Figure 1. This design not only do electrical isolation, but also ensures the data transmission speed.
CAN controller and DSP interface design
SJA1000 data and address signals to time division multiplexing, while the DSP for data and address signal separation structure, and the DSP does not provide ALE signal, the key is to design DSP address SJA1000 should write at the same time as the data generated ALE signal. Required to read and write signals of the shortest effective time, due to low to read data valid for a maximum of 50ns, so read signals to ensure effective for at least 50ns, ADSP21062 in wait with two soft, its low time to 62.5ns (25ns / 2 2 × 25ns), just to meet the requirements.
ADSP21062 and SJA1000 interface to simplify the design
In the case of small peripheral devices connected, the interface circuits can be achieved using several logic gates. As the access to external data, the low 16-bit data bus is not used, so use the data line starting from the DATA16. When Flag1 = 1 时, SJA1000 the WR is always 1, the ALE for the DSP of the WR reverse, when the DSP writes data to addresses as SJA1000, the low level DSP-WR signal is converted into a high level of the ALE, and the falling edge of ALE latches the data. When Flag1 = 0 时, ALE is always 0, no address latch operation. SJA1000, WR directly affected by DSP-WR signal. Flag2 direct control by the CS. The connection shown in Figure 2.
ADSP21062 and SJA1000 simplified interface design of the corresponding procedures are as follows:
1) # define CANADDR 0x400000
2) bit set mode2 FLG1O | FLG2O;
/ / Set Flag1, Flag2 the output
3) r1 = 0x00047800; dm (SYSCON) = r0;
/ / Set the size of outer space
4) r0 = 0x21a8c429; dm (WAIT) = r0;
/ / Wait to visit with two soft-MS0
5) bit set astat ASTAT_FLG1;
/ / Flag1 = 1,
6) r0 = addr; dm (CANADDR) = r0; / / write to internal address to access the SJA1000
7) bit clr astat ASTAT_FLG1;
/ / Flag1 = 0
8) bit clr astat ASTAT_FLG2;
/ / Flag2 = 0, CS = 0
9) i0 = CANADDR; r0 = dm (i0, 0);
/ / Read the corresponding address data SJA1000
10) r1 = 3; dm (i0, 0) = r1;
/ / Write data to the appropriate address SJA1000
11) bit set astat ASTAT_FLG2;
/ / Flag2 = 1, CS = 1,5
To illustrate the convenience of the instruction code. The cost of operating instructions 5,7,8,11 25ns, run the command 6,9,10 the cost 100ns, so complete a read or write be 300ns.
CPLD-based interface design ADSP21062 and SJA1000
When connecting multiple peripheral devices, the decoding circuit is rather complicated, you can use the CPLD logic decoding complete control. CAN signals generated using address data of the ALE, CS and other signals. The advantages of multiple bus devices, the CPLD can be a complete decoding of all bus devices, this method has better applicability. The connection method shown in Figure 3.
DSP programming is as follows:
1) # define CANNCS 0x400100
/ / Clear CANCS address, this address is invalid operation to CAN's CS
2) # define CANCS 0x400200 / / set CANCS address, which address the CS effective action to CAN
3) # define CANALE 0x400500
/ / Set CANALE address, which address the ALE operation can be changed to CAN
4) # define CANNALE 0x400600
/ / Clear CANALE address, which address the ALE CAN constant operation to lower
5) # define CANRW 0x400900
/ / This address operation is complete CAN data reading and writing
6) r1 = 0x00047800; dm (SYSCON) = r0; / / set the outer space
7) r0 = 0x21a8c429; dm (WAIT) = r0;
/ / Wait to visit with two soft-MS0
8) r7 = 0x07; dm (CANALE) = r7;
/ / ALEhigh = 1, CANALE to CANWE of taking anti-
9) r4 = addr; dm (CANRW) = r4;
/ / Write to access the internal register space address SJA1000
10) r7 = dm (CANNALE);
/ / ALEhigh = 0, CANALE total is 0
11) r7 = 0x07; dm (CANCS) = r7;
/ / CANCS = 0
12) r3 = dm (CANRW);
/ / Read the corresponding address data SJA1000
13) r1 = 3; dm (CANRW) = r1;
/ / Write data to the appropriate address SJA1000
14) r7 = dm (CANNCS);
/ / CANCS = 1
The cost of operating instructions 8,9,11,13 100ns, run the command 10,12,14 the cost 75ns, so complete a read or write be 525ns. Faster than before, a simplified design to be a little slower, but this design is more conducive to expansion, for various peripheral interfaces, while saving two Flag pins. When working at maximum speed SJA1000 1Mbit / s, due to be in a data frame into other frames of about 42bit signal, so the completion of 8bit transfer time is about 50 s. The speed of the first two designs were 167 times and 95 times its. Therefore, both the design can meet SJA1000 transmission speed requirements.
CPLD Programming
Figure 4, with 74 138 for decoding, generation ALE, CS and other signals. When the implementation of the Directive 6, set the size of outer space, in the visit will address 0x400000 ~ 0x4fffff time to MS0, 74138 of G2AN will be effective. When the address A11 ~ A8 = 0001, Y1N = 0, CANCS the clear control by the DSP of RD, RD signal low will CANCS = 0, command 11 to complete this feature. When the address A11 ~ A8 = 0010, data D19 ~ D16 = 1000, then Y2N = 0, DSP of the WR signal will CANCS = 1, instruction 14 to complete this function; when the address A11 ~ A8 = 0101, data D19 ~ D16 = 0111, the Y5N = 0, DSP's WR signal along will ALEhigh = 1, then CANWE always maintain 1, CANALE to take anti-WR, instruction 8 to complete this function; when the address A11 ~ A8 = 0110, then Y6N = 0, RD signal low will ALEhigh = 0, then CANALE always remain 0, CANWE for the WR, command 10 to complete this feature.
ADSP21062 only three external interrupts, the number of peripherals linked to resource constraints when they appear. Figure 4, active low or falling edge interrupt signal can be an effective relationship and connected to an interrupt on, DSP in response to failure, read the corresponding number of peripherals, to judge from which peripherals, such can be extended further disruption.
Conclusion
SJA1000 interface address / data multiplexed mode, DSP processors usually address / data bus structure of the separation, this paper provides two different interfaces of the ideas and methods. Tests show that this method is feasible, transmission efficiency.