Output capacitor equivalent series resistance of the hysteresis control of power converters
For experienced circuit designers, they all know that hysteresis control depends on the stability of the power converter output capacitor equivalent series resistance (ESR). If the ESR is too small, then the output voltage ripple will become larger, and would switch signal generator phase shift. Although averaging and linearization techniques in the design and analysis of fixed-frequency PWM power converters on the already well advanced, but the power of the hysteresis loop analytic analysis of the converter is not good. As the operating frequency is variable, and therefore non-linear control theory to analyze the most appropriate.
Output capacitor equivalent series resistance of the hysteresis loop control of power converters
Figure 1 Hysteresis Control Buck Converter
Hysteresis control the operation of the power converter can be summarized as follows. To Figure 1 in the step-down converter, for example, when the output voltage VOUT VREF drop below the threshold, then the switch S1 opens (S2 as the complementary nature of the work). Conversely, when VOUT higher than VREF, then let S1 will be closed. This mode of operation and variable structure control system is similar, it can be based on an ultra-flat (hyper-plane) to transform the control law. Therefore, the variable structure control theory of hysteresis can be controlled best tool for power converters.
Analysis
In order to focus on the impact of RC, assuming inductor ESR is zero, while the switches S1 and S2 are in an ideal situation. When S1 is turned on S2 will be closed.
Output capacitor equivalent series resistance of the hysteresis loop control of power converters (1)
S1 S2 off when they open.
Output capacitor equivalent series resistance of the hysteresis loop control of power converters (2)
Therefore, we obtain,
Output capacitor equivalent series resistance of the hysteresis loop control of power converters (3)
When S1 opens, the value D is 1, and when S1 off that D value is 0. In addition, when S1 is on and off when
iL = iC + Vout / Rout
iL = CdVC / dt +1 / Rout (VC + RCCdVC / dt)
diL / dt = Cd2VC/dt2 +1 / ROUT (dVC / dt + RcCd2VC/dt2)
Substituting equation (3),
Output capacitor equivalent series resistance of the hysteresis loop control of power converters (4)
Hyperplane is defined as follows:
s = VREF-VOUT
= VREF-VC-RCCdVC/dt
Order e = VREF-VC, de / dt =- dVC / dt, d2e/dt2 =- d2VC/dt2
s = e + RCCde / dt (5)
According to hysteresis control the operation of the buck converter, when S1 is turned on, D = 1, if VOUT <VREF,即s> 0; when S1 closed, D = 0, if VOUT> VREF, that is s <0.
Variable structure system based on the analysis, make the following projections.
In order to obtain a stable system, require that when s> 0 时, ds / dt <0; when s <0 时, ds / dt> 0. Therefore, when s> 0, they can meet the ds / dt <0 this condition.
Output capacitor equivalent series resistance of the hysteresis loop control of power converters (7)
Output capacitor equivalent series resistance of the hysteresis loop control of power converters (8)
Which, iC is the output capacitor current, it produces 0A ripple around the steady-state point. Will 2ICMAX iC as the peak ripple current to the peak of the highest value. That when s> 0, we must obtain ds / dt <0 a sufficient condition:
Output capacitor equivalent series resistance of the hysteresis loop control of power converters (9)
Similarly, when s <0, we must obtain ds / dt> 0 sufficient conditions are:
Output capacitor equivalent series resistance of the hysteresis loop control of power converters (10)
The result is RC> max (RCP, RCN)
Analogy
Output capacitor equivalent series resistance of the hysteresis loop control of power converters
Figure 2 When RC = 50mΩ buck converter when the waveform
Output capacitor equivalent series resistance of the hysteresis loop control of power converters
Figure 3 When RC = 5mΩ when the buck converter waveforms
Figures 2 and 3, respectively hysteretic control buck converter waveforms under different RC. Which, VIN = 8V, VREF = 2.5V, L = 10μH, C = 47μF and ROUT = 2.5Ω. For Figures 2 and 3 of the circuit, the output capacitor's equivalent series resistance of 50mΩ and RC were 5mΩ. The figure from the top down the curves represent the VSW, s, iC and VOUT waveform. More stable waveform in Figure 2, when S1 is turned on (when VSW is the high voltage level), s it down; the contrary, when the S1 closed, s will be increased. In this case, ICMAX equal to 0.14A, while the calculated minimum value of RC 11.92mΩ. In other words, a 50mΩ the RC will meet the requirements to give a stable system. However, in terms of the Figure 3, ICMAX equal to 0.9A, according to calculated the minimum requirements for RC 76.59mΩ. Obviously, one can not only 5mΩ the RC to meet the requirements. Can be seen from Figure 3, s not in the S1 on and off after an immediate increase or decrease, but a little bit of time delay. Result, the output voltage ripple will be significantly increased, resulting in a relative phase shift of VSW. This phenomenon is the hysteresis loop buck converter is very common, especially when the output capacitor's ESR is too small.
Conclusion
According to the theory of variable structure control of hysteretic control buck converter, the output voltage ripple increase obtained and the phase shift is due to the small ESR output capacitors due. This explains why the ESR ceramic capacitors are usually smaller in the hysteresis loop does not use step-down converter.