Technology based on short-wave power amplifier predistortion linearization systems
Introduction
With the development of communication technology, linear modulation technology and broadband communication technology is being applied more and more. In the multi-channel short-wave communications transmission equipment, the envelope varies much more than single-sideband modulation signal through the stack, the forming of the broadband signal through a nonlinear RF power amplifier will produce intermodulation component, therefore, must be linear technology to reduce this, resulting in the adjacent channel interference. Pre-distortion technology is a widely used linearization technique, the advantage of flexibility and relatively low complexity.
System Structure
For the short-wave communications, since most use the multi-carrier single sideband modulation, amplitude-sensitive signal, while the phase is not sensitive, so this article assumes that signal, the phase is not sensitive to the basis of the following methods proposed .
This article is based on a lookup table predistorter based, its structure shown in Figure 1. First, according to the results of measurement of power amplifier characteristics, according to an algorithm for establishing pre-distortion coefficient table. Work, the magnitude of the input signal generated by the lookup table of addresses (as amplifier characteristics generally a function of signal amplitude values), and the resulting pre-distortion coefficient, the coefficient multiplying the input signal and to obtain pre-distortion signal.
Technology based on short-wave power amplifier predistortion linearization systems
Figure 1 The structure predistorter
The key pre-distortion technique
The establishment of a lookup table
Ideal amplifier based amplification rate K, corresponding to the signal amplifier of the amplification factor xn as gn, predistorter's coefficients fn. yn = Kxn ideal amplifier corresponds to xn response. By measuring the power amplifier characteristic curve table, can be found when the output amplitude ym = yn corresponding to the input xm, and thus get the following relations: xmgm = Kxn = yn
If the signal after predistortion xn satisfy xnfn = xm, then xnfngm = Kxn
Thus, the system meets the characteristics of an ideal amplifier.
Therefore, the pre-distortion coefficient can be calculated by: fn = xm / xn.
Pre-distortion coefficient table creation process: the input signal xn, calculate the ideal response to yn, and then look through the amplifier characteristics of the table corresponds to the response of the input signal yn xm, the final calculation of pre-distortion coefficient fn = xm / xn
Amplifier Characteristics Measurement
Determination of non-linear characteristics of the power amplifier, its output signal to a nonlinear distortion of the sinusoidal signal, its center frequency set to f0. Of course, it is not a single frequency signal. On the amplifier output signal can not be narrow-band filter, otherwise the nonlinear distortion characteristics undetectable. Secondly, we can not use analog amplitude detection means to determine its magnitude, because the simulation of the effect of detector is not ideal.
On the amplifier output signal only through A / D converter, to measure the parameters of power amplifier distortion, that is, its maximum output signal.
Characteristics of the power amplifier distortion measurement with two characteristics: First, its center frequency can be selected, probably in between 10MHz ~ 15MHz; Second, just obtaining the maximum value measured. Maximum value can not be accumulated or filtering method, as power amplifier output is distorted sinusoidal signal, it will cause distortion to the signal processing.
Set sampling rate high enough, through computer simulation, by ADC precision b = 14 and b = 16 when the two curves (see Figure 2), other parameters the same.
Technology based on short-wave power amplifier predistortion linearization systems
Figure 2 Simulation results of pre-distortion
Shows that the measurement accuracy of the pre-distortion processing effect is obvious, b = 16 the noise level higher than b = 14, sometimes small 6dB.
Limited by the device, when the ADC has high precision, its difficult to make high sample rates.
Convenient for the narrative, set amplifier output y (t) = cos (2 Cheng 0t).
Determination of y (t) the maximum, because the reasons for the sampling rate, the maximum possible error = error
To take full advantage of ADC precision requirement error <1/2b-1, that is 1-cos (? F0 / fs) <1/2b-1
When b = 16, f0 = 11MHz, its phase deviation is less than 0.0087 radians (or 0.5 °), the fs> 4400MHz
This shows that, if a period of a sinusoidal signal is sampled, then the sampling rate is higher than 4400MHz, to ensure the collection to the maximum. This is clearly unrealistic. Can actually lower the signal sampling rate on multiple cycles of continuous sampling, in order to achieve the same effect.
Set y (n) = cos (2 Cheng 0n/fs), if fs is an integer multiple of f0 M, then y (n) = cos (2 Kuang / M),
Each cycle of signal samples collected are the same, whether the maximum value of collected signal depends on the sampling start time. So it is not up purposes.
If fs is not an integer multiple of f0, located fs/f0 = M + p / q, where M is an integer, p, q is relatively prime integers, and p <q, then there is y (n) = cos (2 Kuang / (M + p / q)) = cos (2 Xiao n / (qM + p))
In this case, 0 <n <N, where N = qM + p, q a cycle of continuous sampling, are N different phase of the samples, which is equivalent to a higher sampling rate in a cycle N sampling points.
If the phase difference between adjacent samples is less than 0.5 °, then 360 / N <0.5, ie N <720.
In the design, usually the first M and continuous sampling to determine the number of periods q, finalized p.
Take sampling rate fs = 160/3MHz, since f0 is generally between 10MHz ~ 15MHz, so desirable M = 3 ~ 5. Here take M = 5, q = 144, p in this case desirable 1,5,7,11, ... 143, here to take p = 43, get f0 is 10.0655MHz.
Simulation found that the numerical sampling points ≥ cos (0.5? = 0.9996 two points, namely 239 and 594, which know that conclusion is correct.
Theoretically, the maximum time required to collect N / fs = (qM + p) / (160 / 3) ms = 14.3062ms. Practice, the need to sample much larger than the value of time, here take t = 20 × (N / fs) = 286.124 ≈ 287ms.
Note that 287ms period, the maximum value can be a positive and a negative maximum value, should be selected according to the actual situation of one or choose one from a compromise between the two.
A lower sampling rate on the multi-period continuous sampling signal can be obtained at a higher sampling rate on the effect of a single cycle. This approach solves the problem selection of ADC devices.
Technology based on short-wave power amplifier predistortion linearization systems
System Design
This system is designed as shown in Figure 3.
Clock Distribution: DSP clock provided by a dedicated 10MHz crystal oscillator; other clock from the 40MHz crystal clock via CPLD and FPGA provides: 40MHz all the way into the CPLD, the output frequency through 4, as the AD73322's master clock, the other way into the FPGA, After internal PLL multiplier and frequency divider to generate 80MHz, 160MHz, 160/3MHz clock, respectively, into the ISL5217, AD9777 and AD9244.
The main parameters of each device configuration
AD73322: DMCLK = input clock = 1, sampling rate DMCLK/256 = 39.0625KHz, SCLK = DMCLK / 8.
ISL5217: carrier frequency of 10.0655MHz, carrier frequency phase = 0, the sampling frequency is 39.0625KHz, interpolation multiplier = 16, data input for the parallel port, data output is real, Shaping Filter coefficient settings.
AD9777: interpolating multiple = 2, debug mode is none, dual-port input mode, so to PLL.
FPGA's main work: control module, 2-fold interpolation filter, lookup table, A / D sampling the best value of the search.
System Task
Forward channel: two tasks, one to send test data to the amplifier and the output; Second, the normal data path. ADC sampling rate to 39.0625KHz data, then data to the DSP processing. DSP through the AGC, filtering and modulated to 39.0625KHz rate delivered to the inverter ISL5217, it will be 2048 times the input data interpolation, to 80MHz, and then modulated to the carrier frequency 10.0655MHz sent to FPGA. FPGA will be 2 times its further interpolation, and then pre-distortion. Finally, FPGA pre-distortion of the data will be sent to DAC. DAC will be two-fold interpolation of data processing, data rate up to 320MHz, and then by the DAC output to the amplifier.
Feedback path: Measurement of the characteristics for power amplifier. RF_DA will 160/3MHz sampling rate, sampled data into the FPGA, FPGA to detect the maximum rate of sampling data (positive and negative), and sent them to DSP recorded.
System Workflow
Device Configuration
In the system debugging is completed, the first FPGA in the CCS environment will load the file programmed into Flash memory (only the programming time), in a later work, turned on, the DSP program will load files from the FPGA Flash memory read out by the serial FPGA configuration is loaded into the FPGA, so that the other chips have a clock, and DSP and then configure other devices.
Amplifier Characteristics Measurement
DSP to 39.0625KHz send data, the maximum value from 0 to 32767, each time data is sent continuously 287ms, produce a constant amplitude sine wave, and then read from the FPGA, the most appropriate range of values of the envelope. Note that in the search for the best values, should first send a signal to stabilize in order to ensure the accuracy of the signals detected.
The establishment of a lookup table
Taking into account sampling error, the detected signal is not smooth curves, if the direct use of monitored signals to build the table, the system error is great. Therefore, the sampling of the signal smoothing, which is diverse, not to explain here. As the scope of the sampling signal may be less than -32 767 ~ +32767, to do normalization, and finally start the normal working order.
Conclusion
Predistortion power amplifier linearization to achieve an effective method, its implementation is simple, the system stability. The proposed method is effective and is ideal for a start, use the short application time, because for a long time to change the system temperature, power amplifier temperature drift will cause significant changes in amplifier characteristics, the system performance dramatically for the worse.